class i2c_mst_mon extends uvm_monitor;
    virtual i2c_if vif;
    uvm_analysis_port #(i2c_trans) analysis_port;

    `uvm_component_utils(i2c_mst_mon)

    function new(string name, uvm_component parent);
        super.new(name, parent);
        `uvm_info("TRACE", $sformatf("%m"), UVM_HIGH)
    endfunction

    function void build_phase(uvm_phase phase);
        super.build_phase(phase);
        `uvm_info("TRACE", $sformatf("%m"), UVM_HIGH)

        if (!uvm_config_db#(virtual i2c_if)::get(this, "", "i2c_if", vif)) begin
            `uvm_fatal("CFGERR", "i2c_mst_mon DUT interface not set");
        end
        analysis_port = new("analysis_port", this);
    endfunction

    virtual task run_phase(uvm_phase phase);
        i2c_trans tr;
        `uvm_info("TRACE", $sformatf("%m"), UVM_HIGH)
        wait(vif.rst==0);
        forever begin
            tr = i2c_trans::type_id::create("tr", this);
            get_packet(tr);
            `uvm_info("Got Input Packet", {"\n", tr.sprint()}, UVM_MEDIUM)
            analysis_port.write(tr);
        end
    endtask


    virtual task get_packet(apb_trans tr);
        `uvm_info("TRACE", $sformatf("%m"), UVM_HIGH)

        do begin
            @vif.monclk;
        end
        // need modify following code
        while((vif.monclk.psel &&vif.monclk.penable)==1'b0);
        tr.addr = vif.monclk.paddr;
        if(vif.monclk.pwrite)begin
            tr.data = vif.monclk.pwdata;
            tr.kind = i2c_trans::WRITE;
        end
        else begin
            tr.data = vif.monclk.prdata;
            tr.kind = i2c_trans::READ;
        end
    endtask

endclass